Prior art data encoding methods for encoding digital information have used two voltage levels, where each voltage level represents a single bit. In this respect, a first voltage level represents a digital value "0," while a second voltage level represents a digital value "1." As a result, a set of eight of these voltage levels is needed to encode one byte of digital data. Data bytes are encoded into changing voltages and decoded back into bytes. This is done by using a commonly available electronic device which is generically referred to as a UART (Universal Asyncronous Receiver Transmitter) or an ACIA (Asyncronous Communications Interface Adapter). UARTs convert parallel data (usually eight-bit words) to a serial data stream for transmission over a single wire cable and simultaneously convert a received serial bit stream to parallel words. The serial data stream is comprised of a signal having two voltage levels, one representing a digital "0," the other representing a digital "1."
In many cases, the data rate achievable by UARTs and ACIAs is insufficient for the desired application. In order to achieve greater data rates for high-speed communications, data has been encoded into complex waveforms such as tones, which are then phase, frequency and amplitude modulated. For instance, data has been encoded using RF (Radio Frequency) modulation, QAM (Quadrature Amplitude Modulation), ASK (Amplitude Shift Keying), PSK (Phase Shift Keying), FSK (Frequency Shift Keying), TCM (Trellis Coded Modulation) and QPSK (Quadrature Phase Shift Keying). All of the foregoing methods encode data into AC waveforms for transmission.
The present invention overcomes the data transfer rate limitations of the prior art encoding systems, and provides a system for encoding multiple data bits in parallel as transitions between discrete levels. This encoding system will substantially increase the data transfer rate and conserve bandwidth within a medium which is capable of supporting discrete levels.